In recent times, there has been an increasing need for digital-to-analog converters (DACs) which exhibit extremely high accuracy in converting a digital number to an analog signal, particularly high-speed converters. Accuracy may be expressed in terms of a signal-to-noise ratio (SNR), inaccuracy being equivalent to the introduction of a noise component. DACs with SNRs of more than 100 dB are sought for modem applications. Achieving such accuracy is difficult and costly.
One of the most important influences on DAC output accuracy is the accuracy of the analog weights employed in the converter (i.e., the scaled voltages or currents which combine to form the converter's output). The accuracy of the weights is most often considered from a viewpoint of static performance. Additionally, in high-speed converters, such as those used in sigma-delta DAC output stages, or for video-speed converters, dynamic effects are often just as important as static accuracy. These dynamic effects are characterized by, or attributable to, the way in which the DAC makes a transition from one digital code to the next. A DAC with poor dynamic performance will produce high distortion, as shown on a spectrum analyzer, even though the analog weights may be very accurate.
While a number of factors affect the dynamic performance of a DAC, inter-symbol interference (ISI) is one of the most important. In this context, ISI occurs when the DAC output waveform for a particular clock period is a function not only of the digital code applied to the DAC for that clock period, but also of the digital code applied for a preceding clock period. This interference can cause both distortion and noise to appear at the DAC output.
In a DAC, ISI manifests itself by the area under the DAC output waveform for a given clock period (i.e., the time integral of the output) depending partly on the applied digital code (i.e., input signal value) during the previous clock period. In such a DAC, the accuracy of the area under the output waveform curve for a selected output sample is an extremely important measure of performance, as it contributes heavily to the purity of the low-frequency part of the output spectrum. That is, the output of an n-bit DAC comprises the sum of "n" analog waveforms, taking the form of a voltage or a current. In order for the DAC output to be free of ISI, each individual constituent analog bit waveform thus must be free of ISI (the output being a linear summation of the constituent waveforms).
The problem is illustrated with reference to FIGS. 1 and 2. In FIG. 1 there is shown a block diagram of a typical output stage 10 for a DAC whose output is an analog current (actually a differential current pair Iout+ and Iout-). The output signal is generated by a set of weighted current sources 12.sub.0 . . . 12.sub.N, where N is the number of bits in the DAC's digital input code, there being one switch per bit. The currents from the current sources are selectively switched into the output to contribute to the output signal via a corresponding set of switches 14.sub.0 . . . 14.sub.N. The settings of the switches are determined by control logic 16 each time a clock signal is received, in accordance with a digital input code supplied thereto. The switches are typically switched on an edge of the clock signal.
One significant mechanism which gives rise to ISI may be understood by considering the output contribution of the source 12.sub.0, which is driven by the most significant bit (MSB), bit 0. ISI may result from unequal rise and fall times in the MSB output current contribution from source 12.sub.0. As shown in part A of FIG. 2, the rising clock edges are active clock edges (i.e., edges to which the switches respond) and occur at times T1, T2, etc. The time interval between two consecutive active clock edges is called a bit clock period and is the time during which a particular signal sample is valid. (It is equal in length to a cycle of the clock signal.) The data may take a finite time, of course, to reach a settled value, due to rise time and fall time limitations.
Assume that for the three clock intervals T1-T2, T2-T3 and T3-T4, the MSB pattern is 110. Assuming the previous bit was a 0, the waveform I.sub.0 at the output of switch 14.sub.0 thus rises, starting at time T1, for a rise time T.sub.rise, until it reaches a value I.sub.ref. It holds this value, which represents a digital one, until time T3. At time T3, the bit value goes to zero but the analog current I.sub.0 cannot change instantaneously so it falls over an interval T.sub.fall until it is back to zero. Now consider the situation when for the three clock intervals T1-T2, T2-T3 and T3-T4, the MSB pattern is 101. The resulting waveform for I.sub.0 is shown in part B of FIG. 2. The area under waveform I.sub.0 of part A is given by (T4-T1)*I.sub.ref -.5*T.sub.rise *I.sub.ref +.5T.sub.fall *I.sub.ref ; in contrast, the area under waveform I.sub.0 of part B is given by (T4-T1)*I.sub.ref -T.sub.rise *I.sub.ref +T.sub.fall *I.sub.ref. Only if T.sub.rise and T.sub.fall are equal will the areas under the waveforms of parts A and B of FIG. 2 be equal. When T.sub.rise and T.sub.fall are unequal, the low-frequency spectra of the two waveforms will be different. The DAC output is quite sensitive to this error. Indeed, for a typical oversampled audio converter (e.g., a sigma delta converter), high performance may require that T.sub.rise and T.sub.fall be matched to less than ten picoseconds.
Conventionally, this kind of ISI is reduced by forcing the output bit to start from zero, reach its final value, and return to zero all within a single bit clock period (clock cycle). This is called a "return-to zero" (RTZ) code. Since there is a rise and a fall within every clock cycle, the area under each waveform pulse is guaranteed to be independent from prior bit values.
Unfortunately, the RTZ approach is not without its limitations. FIG. 3 shows a conventional DAC output 22, with the rise and fall times exaggerated to show a mismatch between them. The corresponding output waveform when an RTZ scheme is employed is shown at 24 in FIG. 4. The reader will observe that the RTZ scheme introduces full-scale steps into the output waveform. This potentially degrades performance or causes problems in two ways. First, the operation of a circuit connected to receive the DAC output may become non-linear when driven by such large, high-speed steps. Second, any error in the clock edge timing, due to jitter or other mechanisms, may produce a large error in the output due to the large step size. In oversampled DACs, this is a particularly egregious problem because sample-to-sample output current or voltage differences normally would be a small fraction of the full-scale range of the converter; however, using an RTZ scheme, the average step size may be dramatically larger and the sensitivity to clock jitter may therefore be degraded seriously. Additionally, increased filtering is needed in order to obtain a smooth output waveform for subsequent utilization.
Thus a need exists for an output stage architecture for a DAC, particularly an oversampled DAC, which provides both high static accuracy and high dynamic accuracy. Such an output stage must be capable of high speed operation with very low intersymbol interference levels.